1. Field of the Invention
The present invention relates to an inverter, buffer, and level shifter, and to a semiconductor device using them. Note that the term display device used within this specification includes a liquid crystal display device which employ liquid crystal elements in pixels, and a light emitting device which employ light emitting elements such as electro-luminescence (EL) elements. The term semiconductor device indicates circuits that perform processing for inputting video signals into pixels disposed in the display device and displaying images. Pulse output circuits such as shift registers, inverters, buffers, and level shifters, and amplification circuits such as amplifiers are included in the category of semiconductor devices.
2. Description of the Related Art
In recent years, display devices manufactured by forming semiconductor thin films on an insulator such as a glass substrate, in particular, active matrix display devices such as LCDs (liquid crystal displays) using thin film transistors (hereinafter referred to as TFTs), are being utilized in many manufactured products, and are spreading. The active matrix display devices using TFTs have from several hundred thousands to several million pixels arranged in a matrix shape, and display of images is performed by controlling the electric charge of each pixel with TFTs disposed in the respective pixels.
In addition, techniques related to polysilicon TFTs for TFTs have been developed recently, and a driver circuit using TFTs is formed in a peripheral region of a pixel portion on a substrate simultaneously with pixel TFTs structuring pixels. The techniques contribute greatly to making a device small size and to reducing electric power consumption, and accordingly, a display device has come to be indispensable for a portion such as a display portion of a mobile information terminal, which has remarkably been applied to the extensive fields in recent years.
In general, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined are used as a circuit for structuring semiconductor devices. A CMOS inverter is shown in FIG. 11A as one example of the CMOS circuit. A p-channel TFT 1101 and an n-channel TFT 1102 are combined, and an output signal is obtained by inverting the polarity of an input signal (see FIG. 11B).
Now, as shown in FIG. 11C, there is a state in which a certain load (Load) is attached to the later stage of the CMOS inverter. If the load is excessive with respect to the size of the TFTs structuring the CMOS inverter at this point and a pulse is input from an input (In), there will be a case in which an output pulse, namely an output (Out i) of an inverter (Inv1) in FIG. 11C, is greatly dulled in both rise and fall of the pulse, compared to the waveform of the input signal, as shown in FIG. 11E. This is because the CMOS itself inverter does not have the capability of supplying a sufficient amount of electric charge for driving the load.
There normally is lot of weight given to low electric power consumption with semiconductor devices, and logical circuits are structured using relatively small size TFTs. On the other hand, display regions are becoming larger in size, and in addition, the number of pixels is increasing. The load due to the pixels is therefore large. As stated above, pulses are not output normally if a large load is present in the later stage of an inverter with a small driving capability.
A buffer is normally formed between a driver circuit portion and a pixel portion. Typically, a plurality of inverter stages are disposed in series as shown in FIG. 11D, and driving of the final load can be performed without problem by driving the inverters that are gradually increased in size. Compared to the structure of FIG. 11C, the waveform of an output (Out ii) of a buffer in the final stage (Inv4) is not greatly dulled and thus is output as a normal pulse, and the load in the later stage can be driven.
Display devices have come to be employed in the display portion of many types of electronic devices in recent years, and there is steady expansion in the number of fields in which display devices are used. Display devices are recently being actively employed even in relatively low cost electronic equipment, and therefore further cost reductions are desirable.
A multiple-layer structure is formed for a display device by repeatedly performing processes of film formation, exposure to light using a photomask, and etching. The extreme complexity of the processes therefore invites an increase in manufacturing costs. In addition, in the case in which the driver circuit and the pixel portion are formed integrally on the substrate as discussed above, some defects become a problem which affects the entire manufactured product, and has a large influence on yield.
A method in which the number of processes is reduced as much as possible, and manufacturing can be performed simply in a short period of time can be given as one method of achieving the cost reduction. A display device is manufactured with a structure that uses TFTs with a single polarity type, n-channel TFTs or p-channel TFTs, instead of a CMOS structure for the driver circuit. Processes for adding an impurity which imparts a conductivity to a semiconductor layer can thus be simply cut in half, and in addition, the number of photomasks can be reduced. This is extremely effective from the vie point of cost-related merits.
A conventionally known single polarity type circuit is explained here.
FIG. 12A shows an example in which an inverter is structured by two n-channel TFTs. The inverter is a two input type inverter with signals input to gate electrodes of TFTs 1201 and 1202. An inverted signal of one input is used as the other input.
Operation of the inverter shown in FIG. 12A is explained simply here. Note that the terms xe2x80x9cgate electrode, input terminal, and output terminalxe2x80x9d, and the terms xe2x80x9cgate electrode, source region, and drain regionxe2x80x9d are used separately in this specification for the names of the three electrodes of the TFT in explaining the circuit structure and operation. This is because, although there are many cases in which the voltage between the gate and the source is considered in explaining TFT operation, it is difficult to clearly differentiate the source region and the drain region of the TFT based upon the structure of the TFT and the use of unified names may, instead of being helpful, lead to confusion developing. The terms input terminal and output terminal are used in explaining the input and output of signals. The input terminal or the output terminal is referred to as the source region, and the other is referred to as the drain region, in explaining the relationship of the electric potential between the electrodes of the TFT.
First, operation of the two input inverter of FIG. 12A is explained. When H level is input to a first input (In) and L level is input to a second input (Inb), the TFT 1201 turns off and the TFT 1202 turns on. L level therefore appears in an output (Out) and the electric potential of the output becomes VSS. On the other hand, when L level is input to the first input (In), and H level is input to the second input (Inb), the TFT 1201 turns on and the TFT 1202 turns off. H level therefore appears in the output (Out) to pulled up to the VDD side.
At this point, the electric potential is considered when the output (Out) become the H level.
The L level is input to the gate electrode of the TFT 1202 when the H level is input to the gate electrode of the TFT 1201 in FIG. 12A. The TFT 1201 is therefore on, and the TFT 1202 is therefore off. Accordingly, the electric potential of the output (Out) begins to rise, and the voltage between the gate and the source of the TFT 1201 becomes equal to the threshold value VthN when the electric potential of the output (Out) becomes (VDDxe2x88x92VthN). That is, the TFT 1201 turns off at this instant, and therefore the electric potential of the output (Out) cannot rise any further.
A circuit in which a plurality of stages of the inverters shown FIG. 12A are connected in series is shown in FIG. 12B. The output of a certain stage becomes the input of the next stage with this type of circuit. As discussed above, waveforms in which the amplitude is attenuated by VthN with respect to the input signal appear in an output (Out i) of a first stage and an output (Out ii) of the next stage. An output (Out iii) of a third stage is additionally attenuated by VthN compared with the first stage output (FIG. 12C). Similarly, attenuation of the amplitude due to the threshold voltage continues to develop and overlap throughout the stages, the amplitude of the waveform shrinks rapidly, and the circuit cannot function as a satisfactory circuit.
A boot strap method is known in order to resolve this problem in structuring the circuit by using single polarity type TFTs. A basic circuit which functions by using the boot strap method is shown in FIG. 13A.
FIG. 13A is an inverter structured by three n-channel TFTs 1301 to 1303 and a capacitor means 1304, as disclosed in JP 3092595 B. A signal is input to a gate electrode of the TFT 1303, and the inverted signal of the signal is input to an input terminal of the TFT 1301.
Operation is explained. The amplitude of the input signal is VDD to VSS here. Refer to FIG. 13A and FIG. 13B. FIG. 13B is a diagram showing an input signal (In), an electric potential (Vf) of a gate electrode of the TFT 1302, and an output signal (Out).
When a H level signal is input to the input (In), and a L level signal is input to the inverted input (Inb), the electric potential of the gate electrode of the TFT 1301 is VDD to be in an on state, and therefore the electric potential of the gate electrode of the TFT 1302 is L level to turn off. On the other hand, the H level is input to the gate electrode of the TFT 1303 to turn on, and L level appears at the output (Out).
When a L level signal is input to the input (In), and an H level signal is input to the inverted input (Inb), the electric potential of the gate electrode of the TFT 1301 is VDD to be in an on state, and therefore the electric potential of the gate electrode of the TFT 1302 is H level. However, the electric potential of the gate electrode of the TFT 1301 is VDD, and therefore the electric potential of an output terminal of the TFT 1301, that is the electric potential of the gate electrode of the TFT 1302, becomes (VDDxe2x88x92VthN) to place the TFT 1301 in an off state. The gate electrode of the TFT 1302 is thus placed in a floating state at this instant. On the other hand, the TFT 1303 turns off.
The voltage between the gate and the source of the TFT 1302 rises above the TFT threshold voltage, the TFT 1302 therefore turns on, and the electric potential of an output terminal of the TFT 1302 is pulled up the to VDD side. However, the electric potential of the gate electrode of the TFT 1302 is (VDDxe2x88x92VthN) at this point, and the electric potential of the output terminal of the TFT 1302 can thus only increase to (VDDxe2x88x922VthN).
The capacitor 1304 is formed between the output terminal and the gate electrode of the TFT 1302, however, and the gate electrode of the TFT 1302 is in a floating state. Therefore the electric potential of the gate electrode of the TFT 1302 rises by xcex94Vf shown in (ii) of FIG. 13B due to capacitive coupling along with the rise in the electric potential of the output terminal of the TFT 1302. The electric potential of the gate electrode of the TFT 1302 is thus greater than (VDD+VthN), and therefore the electric potential of the output terminal of the TFT 1302 then becomes equal to VDD. Note that a dotted line denoted by reference numeral 1350 in (iii) of FIG. 13B is an output example in the case of using the inverter shown in FIGS. 12A and 12B.
The inverter shown in FIG. 13A outputs an inverted signal without amplitude attenuation due to the threshold value of the TFT by the aforementioned procedure. A method of operating the electric potential of a node in a floating state by utilizing capacitive coupling between two nodes is referred to as a boot strap method.
It takes time for charging a load in the case in which the load attached to the later stage is large in an inverter that uses a boot strap method, and therefore the rise time becomes long. It is possible to increase the effect of the boot strap by making the capacitor 1304 larger. Conversely, however, a delay in the increase of the electric potential of the output with respect to the input becomes long if the capacitor is made too large, thus the size of the capacitor is limited.
The rise time may become long, or the boot strap may not function sufficiently and the amplitude of the output signal may not be able to be normalized (specifically, H level may not be sufficiently brought up), in the cases in which the load attached to the later stage of the output is additionally large, the amplitude of the input signal is small (H level is low), the threshold value of the TFT is large, and parasitic capacitance in the gate electrode of the TFT in a floating state is large during boot strap operations, and similar cases.
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a circuit which with a high load driving capability, which is structured to make a rise time short and to make the amplitude of an output signal normal in cases stated above.
As shown in FIG. 1A, there is a structure in which two TFTs are added to the structure of FIG. 13A. The TFTs 1302 and 1303 in FIG. 13A have roles for boot strap operation and for electrical charge and discharge of a load of a latter stage. However, TFTs 102 and 103 contribute only to boot strap operations in the structure shown in FIG. 1A, and TFTs 105 and 106 are formed as TFTs that perform electrical charge and discharge of a load. With such structure, it is possible to obtain good operation with no loss of function even in the case in which the load attached to a later stage becomes somewhat large.
In FIG. 1A, the electric potential of a gate electrode of the TFT 102 in a floating state is taken as V1, and the electric potential of an output electrode of the TFT 102 at this time is taken as V2. A capacitor 104 and a capacitance due to parasitic capacitance and the like exist in the gate electrode of the TFT 102, and their values are taken as C1 and C0, respectively.
V2 fluctuates from V2(0) to V2(1) (where V2(0) less than V2(1)). If the value of this fluctuation is taken as xcex94V2, the electric potential of V1 also fluctuates from V1(0) to V1(1) (where V1(0) less than V1(1)) due to capacitive coupling of C1. If the value of the fluctuation is taken as xcex94V1, the relationship can be shown by the following equation:
xcex94V1=xcex94V2[C1/(C0+C1)]xe2x80x83xe2x80x83(Eq. 1)
There are two ways for increasing xcex94V1, namely increasing the amount of the fluctuation in the electric potential of the gate electrode of the TFT 102 in a floating state: (1) increasing the value of [C1/(C0+C1)], and (2) increasing xcex94V2. In the former case, the coupling capacitance C1 between the gate electrode and the output electrode of the TFT 102 sufficiently is made large with respect to the parasitic capacitance C0. In the latter case, xcex94V2=[V2(1)xe2x88x92V2(0)], and therefore a method of reducing V2(0) and a method of increasing V2(1) can be considered. It is difficult to increase V2(1) to be equal to or greater than VDD with this structure, and therefore the method of reducing V2(0) is employed.
The voltage between a gate and a source of the TFT 102 can be increased by reducing V2(0), and a larger amount of drain current can be made to flow. Shortening of the rise time can thus be expected.
In order to achieve such means, as shown in FIG. 1B, a capacitor means 155 is formed between a gate electrode and an output terminal of a TFT 153 in addition to a capacitor means 154 formed between a gate electrode and an output terminal of a TFT 152.
The load driving capability can be increased with such structure, and therefore the number of stages for buffers and the like can be made smaller, which lead to redaction in the surface area occupied by circuits.
The driver circuit and the pixel portion can be structured by using TFTs with the single polarity, and therefore a portion of processes for adding impurity elements to semiconductor layers can be omitted in a process of manufacturing a display device.
Structures of the present invention are described below.
A semiconductor device according to the present invention is characterized by comprising:
first and second transistors each comprising an input terminal electrically connected to a first electric power source;
third and fourth transistors each comprising an input terminal electrically connected to a second electric power source;
a voltage compensator circuit comprising: a fifth transistor comprising an output terminal electrically connected to a gate electrode of the first transistor and a gate electrode of the second transistor; and a capacitor between the output terminal of the fifth transistor and an output terminal of the first transistor;
a first signal input portion for inputting a first signal to a gate electrode of the third transistor and a gate electrode of the fourth transistor;
a second signal input portion for inputting a second signal to an input terminal of the fifth transistor; and
a signal output portion,
in which:
each of the first through the fifth transistors have the same conductivity type,
the output terminal of the first transistor and an output terminal of the third transistor are electrically connected,
an output terminal of the second transistor and an output terminal of the fourth transistor are electrically connected to the signal output portion,
a gate electrode of the fifth transistor is electrically connected to the first electric power source or to a third electric power source, and
the voltage compensator circuit compensates for amplitude attenuation of a signal output from the signal output portion.
A semiconductor device according to the present invention is characterized by comprising:
first and second transistors each comprising an input terminal electrically connected to a first electric power source;
third and fourth transistors each comprising an input terminal electrically connected to a second electric power source;
a voltage compensator circuit comprising: a fifth transistor comprising an output terminal electrically connected to a gate electrode of the first transistor and a gate electrode of the second transistor; a first capacitor between a gate electrode of the first transistor and an output terminal of the first transistor; and a second capacitor between a gate electrode of the third transistor and an output terminal of the third transistor;
a first signal input portion for inputting a first signal to a gate electrode of the third transistor and a gate electrode of the fourth transistor;
a second signal input portion for inputting a second signal to an input terminal of the fifth transistor; and
a signal output portion,
in which:
each of the first through the fifth transistors have the same conductivity type,
the output terminal of the first transistor and the output terminal of the third transistor are electrically connected,
an output terminal of the second transistor and an output terminal of the fourth transistor are electrically connected to the signal output portion,
a gate electrode of the fifth transistor is electrically connected to the first electric power source or to a third electric power source, and
the voltage compensator circuit compensates for amplitude attenuation of a signal output from the signal output portion.
The semiconductor device according to the present invention is characterized in that the capacitor is formed by:
two electrodes selected from the group consisting of an active layer, a gate electrode, and a wiring; and
an insulating material between the two electrodes.
The semiconductor device according to the present invention is characterized in that one of the first and second capacitor means is formed by:
two electrodes selected from the group consisting of an active layer, a gate electrode, and a wiring; and
an insulating material between the two electrodes.
The semiconductor device according to the present invention is characterized in that:
electric potential of the second electric power source is less than electric potential of the first electric power source when the conductivity type is n-channel, and
the electric potential of the second electric power source is more than the electric potential of the first electric power source when the conductivity type is p-channel.
The semiconductor device according to the present invention is characterized in that:
electric potential of the third electric power source is more than electric potential of the second electric power source and less than electric potential of the first electric power source when the conductivity type is n-channel, and
the electric potential of the third electric power source is less than the electric potential of the second electric power source and more than the electric potential of the first electric power source when the conductivity type is p-channel.
A semiconductor device according to the present invention is characterized by comprising:
first and second transistors each comprising an input terminal electrically connected to a first electric power source;
third and fourth transistors each comprising an input terminal electrically connected to a second electric power source;
a voltage compensator circuit comprising: a fifth transistor comprising an input terminal electrically connected to the first electric power source and an output terminal electrically connected to a gate electrode of the first transistor and a gate electrode of the second transistor; a sixth transistor comprising an input terminal electrically connected to the second electric power source and an output terminal electrically connected to the gate electrode of the first transistor and the gate electrode of the second transistor; and a capacitor between the gate electrode and an output terminal of the first transistor;
a first signal input portion for inputting a first signal to a gate electrode of the third transistor, a gate electrode of the fourth transistor, and a gate electrode of the sixth transistor;
a second signal input portion for inputting a second signal to an input terminal of the fifth transistor; and
a signal output portion,
in which:
each of the first through the sixth transistors have the same conductivity type,
the output terminal of the first transistor and an output terminal of the third transistor are electrically connected,
an output terminal of the second transistor and an output terminal of the fourth transistor are electrically connected to the signal output portion,
a gate electrode of the fifth transistor is electrically connected to the first electric power source or to a third electric power source, and
the voltage compensator circuit compensates for amplitude attenuation of a signal output from the signal output portion.
A semiconductor device according to the present invention is characterized by comprising:
first and second transistors each comprising an input terminal electrically connected to a first electric power source;
third and fourth transistors each comprising an input terminal electrically connected to a second electric power source;
a voltage compensator circuit comprising: a fifth transistor comprising an input terminal electrically connected to the first electric power source and an output terminal electrically connected to a gate electrode of the first transistor and a gate electrode of the second transistor; a sixth transistor comprising an input terminal electrically connected to the second electric power source and an output terminal electrically connected to the gate electrode of the first transistor and the gate electrode of the second transistor; a first capacitor between the gate electrode and an output terminal of the first transistor; and a second capacitor between a gate electrode and an output terminal of the first transistor;
a first signal input portion for inputting a first signal to the gate electrode of the third transistor, a gate electrode of the fourth transistor, and a gate electrode of the sixth transistor;
a second signal input portion for inputting a second signal to an input terminal of the fifth transistor; and
a signal output portion,
in which:
each of the first through the sixth transistors have the same conductivity type,
the output terminal of the first transistor and an output terminal of the third transistor are electrically connected,
an output terminal of the second transistor and an output terminal of the fourth transistor are electrically connected to the signal output portion,
a gate electrode of the fifth transistor is electrically connected to the first electric power source or to a third electric power source, and
the voltage compensator circuit compensates for amplitude attenuation of a signal output from the signal output portion.
The semiconductor device according to the present invention is characterized in that the capacitor is formed by:
two electrodes selected from the group consisting of an active layer, a gate electrode, and a wiring; and
an insulating material between the two electrodes.
The semiconductor device according to the present invention is characterized in that one of the first and second capacitor means is formed by:
two electrodes selected from the group consisting of an active layer, a gate electrode, and a wiring; and
an insulating material between the two electrodes.
The semiconductor device according to the present invention is characterized in that:
wherein electric potential of the second electric power source is less than electric potential of the first electric power source when the conductivity type is n-channel, and
wherein the electric potential of the second electric power source is more than the electric potential of the first electric power source when the conductivity type is p-channel.